56 lines
1.5 KiB
VHDL
56 lines
1.5 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity randgen is
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port(address : in std_logic_vector(15 downto 0);
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read : in std_logic;
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rddata : out std_logic_vector(31 downto 0);
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clk : in std_logic;
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reset_n : in std_logic);
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end entity randgen;
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architecture rtl of randgen is
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constant addr_map : std_logic_vector(15 downto 0) := x"2010";
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signal rand_q : std_logic_vector(31 downto 0);
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signal rand_next : std_logic_vector(31 downto 0);
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signal cs : std_logic;
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begin
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reg:process(clk, reset_n) is
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begin
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if(reset_n = '0') then
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rand_q <= (others => '0');
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elsif(rising_edge(clk)) then
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rand_q <= rand_next;
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end if;
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end process reg;
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lfsr:process(rand_q) is
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begin
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if rand_q = x"00000000" then
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rand_next <= x"55555555";
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else
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rand_next <= rand_q(30 downto 0) & rand_q(31);
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rand_next(2) <= rand_q(1) xor rand_q(31);
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rand_next(6) <= rand_q(5) xor rand_q(31);
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rand_next(7) <= rand_q(6) xor rand_q(31);
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end if;
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end process lfsr;
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chipsel:process(clk, reset_n) is
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--One cycle latency.
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begin
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if(reset_n = '0') then
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cs <= '0';
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elsif(rising_edge(clk)) then
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if(address = addr_map and read = '1') then
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cs <= '1';
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else
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cs <= '0';
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end if;
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end if;
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end process chipsel;
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rddata <= rand_q when cs = '1' else (others => 'Z');
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end architecture rtl;
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