20 lines
357 B
VHDL
20 lines
357 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity mux2x16 is
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port(
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i0 : in std_logic_vector(15 downto 0);
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i1 : in std_logic_vector(15 downto 0);
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sel : in std_logic;
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o : out std_logic_vector(15 downto 0)
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);
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end mux2x16;
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architecture synth of mux2x16 is
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begin
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o <= i0 when sel = '0' else
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i1;
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end synth;
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