56 lines
1.3 KiB
VHDL
56 lines
1.3 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RAM is
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port(
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clk : in std_logic;
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cs : in std_logic;
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read : in std_logic;
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write : in std_logic;
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address : in std_logic_vector(9 downto 0);
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wrdata : in std_logic_vector(31 downto 0);
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rddata : out std_logic_vector(31 downto 0));
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end RAM;
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architecture synth of RAM is
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signal reg_read : std_logic;
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signal reg_address : std_logic_vector(9 downto 0);
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type reg_type is array(0 to 1023) of std_logic_vector(31 downto 0);
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signal reg: reg_type := (others => (others => '0'));
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begin
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-- registers
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process(clk)
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begin
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if (rising_edge(clk)) then
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reg_read <= cs and read;
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reg_address <= address;
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end if;
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end process;
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-- read
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process(reg_read, reg_address, reg)
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begin
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rddata <= (others => 'Z');
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if (reg_read = '1') then
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rddata <= reg(to_integer(unsigned(reg_address)));
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end if;
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end process;
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-- write
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process(clk)
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begin
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if (rising_edge(clk)) then
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if (cs = '1' and write = '1') then
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reg(to_integer(unsigned(address))) <= wrdata;
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end if;
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end if;
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end process;
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end synth;
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