29 lines
515 B
VHDL
29 lines
515 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity IR is
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port(
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clk : in std_logic;
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enable : in std_logic;
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D : in std_logic_vector(31 downto 0);
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Q : out std_logic_vector(31 downto 0)
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);
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end IR;
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architecture synth of IR is
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signal sq : std_logic_vector(31 downto 0) := (others => '0');
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begin
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write : process(clk, enable) is
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begin
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if (rising_edge(clk) and enable = '1') then
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sq <= D;
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end if;
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end process;
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Q <= sq;
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end synth;
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