432 lines
30 KiB
VHDL
432 lines
30 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.check_functions.all;
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entity tb_Controller is
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generic(
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text_in : string := "Controller/in.txt"
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);
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end;
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architecture testbench of tb_Controller is
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signal finished : boolean := false;
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signal currenttime : time := 0 ns;
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constant FETCH1 : integer := 0;
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constant FETCH2 : integer := 1;
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constant DECODE : integer := 2;
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constant R_OP : integer := 3;
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constant RI_OP : integer := 4;
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constant I_OP : integer := 5;
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constant UI_OP : integer := 6;
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constant LOAD1 : integer := 7;
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constant LOAD2 : integer := 8;
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constant STORE : integer := 9;
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constant BRANCH : integer := 10;
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constant CALL : integer := 11;
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constant CALLR : integer := 12;
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constant JMP : integer := 13;
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constant BREAK : integer := 14;
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constant JMPI : integer := 15;
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constant HI_OP : integer := 16;
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signal state : integer := FETCH1;
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signal pc_counter : integer := 0;
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component controller is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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op : in std_logic_vector(5 downto 0);
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opx : in std_logic_vector(5 downto 0);
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branch_op : out std_logic;
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imm_signed : out std_logic;
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ir_en : out std_logic;
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pc_add_imm : out std_logic;
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pc_en : out std_logic;
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pc_sel_a : out std_logic;
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pc_sel_imm : out std_logic;
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rf_wren : out std_logic;
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sel_addr : out std_logic;
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sel_b : out std_logic;
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sel_mem : out std_logic;
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sel_pc : out std_logic;
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sel_ra : out std_logic;
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sel_rC : out std_logic;
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read : out std_logic;
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write : out std_logic;
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op_alu : out std_logic_vector(5 downto 0)
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);
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end component;
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constant CLK_PERIOD : time := 5 ns;
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal op : std_logic_vector(5 downto 0);
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signal opx : std_logic_vector(5 downto 0);
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signal branch_op : std_logic;
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signal imm_signed : std_logic;
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signal ir_en : std_logic;
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signal pc_add_imm : std_logic;
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signal pc_en : std_logic;
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signal pc_sel_a : std_logic;
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signal pc_sel_imm : std_logic;
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signal rf_wren : std_logic;
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signal sel_addr : std_logic;
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signal sel_b : std_logic;
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signal sel_mem : std_logic;
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signal sel_pc : std_logic;
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signal sel_ra : std_logic;
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signal sel_rC : std_logic;
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signal reads : std_logic;
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signal write : std_logic;
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signal op_alu : std_logic_vector(5 downto 0);
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signal reg_read : std_logic;
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signal sel_addr_reg : std_logic;
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function to_integer(x : std_logic) return integer is
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begin
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if x = '0' then
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return 0;
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else
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return 1;
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end if;
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end function to_integer;
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begin
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controller_0 : controller port map(
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clk => clk,
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reset_n => reset_n,
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op => op,
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opx => opx,
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branch_op => branch_op,
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imm_signed => imm_signed,
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ir_en => ir_en,
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pc_add_imm => pc_add_imm,
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pc_en => pc_en,
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pc_sel_a => pc_sel_a,
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pc_sel_imm => pc_sel_imm,
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rf_wren => rf_wren,
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sel_addr => sel_addr,
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sel_b => sel_b,
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sel_mem => sel_mem,
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sel_pc => sel_pc,
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sel_ra => sel_ra,
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sel_rC => sel_rC,
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read => reads,
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write => write,
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op_alu => op_alu
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);
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check : process
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constant filename : string := "Controller/report.txt";
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file text_report : text is out filename;
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file text_input : text is in text_in;
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variable line_output : line;
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variable line_input : line;
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variable counter : integer := 0;
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variable timeout : integer := 0;
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variable success : boolean := true;
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variable op_alu_mask : std_logic_vector(5 downto 0);
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variable op_alu_cmp : std_logic_vector(5 downto 0);
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variable INT : integer;
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variable SINGLE_BIT : std_logic;
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variable NIBBLE : std_logic_vector(7 downto 0);
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begin
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line_input := new string'("");
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if (endfile(text_input)) then
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finished <= true;
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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if (success) then
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line_output := new string'("Simulation is successful");
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else
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line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
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end if;
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writeline(output, line_output);
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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wait;
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end if;
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counter := counter + 1;
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readline(text_input, line_input);
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if (line_input'length /= 0) then
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if (line_input(1) = '-') then -- Print message
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line_output := line_input;
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writeline(output, line_input);
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elsif (line_input(1) /= '#') then
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wait until clk = '1';
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read(line_input, SINGLE_BIT);
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reset_n <= SINGLE_BIT;
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hread(line_input, NIBBLE);
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op <= NIBBLE(5 downto 0);
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hread(line_input, NIBBLE);
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opx <= NIBBLE(5 downto 0);
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read(line_input, INT);
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state <= INT;
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read(line_input, op_alu_mask);
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read(line_input, op_alu_cmp);
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wait until clk = '0';
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-- op_alu
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if (unsigned(op_alu_mask) /= 0) then
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success := scheck(op_alu and op_alu_mask, op_alu_cmp and op_alu_mask, "op_alu", filename, counter, currenttime, " Verify the op_alu generation.") and success;
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end if;
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-- valid instruction when ir_en
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if (sel_addr_reg = '1') then
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success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " The IR has been enabled too soon.") and success;
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end if;
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-- unconditional branch
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if (state = BRANCH and unsigned(op) = 6) then
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if (pc_en = '0') then
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success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
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if (op_alu /= "011001" and (op_alu /= "011100" and op_alu /= "011101")) then
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assert false
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report "br: Make sure that with the given op_alu value, the ALU will always return 1."
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severity WARNING;
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end if;
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end if;
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end if;
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case state is
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when FETCH1 =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During FETCH, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During FETCH, rf_wren has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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when FETCH2 =>
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timeout := 0;
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loop
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During FETCH, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During FETCH, rf_wren has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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if (ir_en = '0') then
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if (timeout = 10) then
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finished <= true;
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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line_output := new string'("IR has not been activated... Simulation aborted.");
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writeline(output, line_output);
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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wait;
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end if;
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else
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success := bcheck(reg_read, '1', "read", filename, counter, currenttime, " Before activating ir_en, read has to be activated.") and success;
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exit;
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end if;
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wait until clk = '0';
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timeout := timeout + 1;
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end loop;
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when DECODE =>
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success := icheck((pc_counter + to_integer(pc_en)), 1, "PC enable count", filename, counter, currenttime, " Before the Execute states, the PC must be enabled only once.") and success;
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During DECODE, write has to be 0.") and success;
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success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During DECODE, rf_wren has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During FETCH, branch_op has to be 0.") and success;
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if (pc_en = '1') then
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success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " Before the Execute states, PC must be incremented of 4.") and success;
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end if;
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when R_OP =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During R_OP, write has to be 0.") and success;
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success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During R_OP, pc_en has to be 0.") and success;
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success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During R_OP, ir_en has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During R_OP, branch_op has to be 0.") and success;
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success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During R_OP, sel_mem has to be 0.") and success;
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success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During R_OP, sel_pc has to be 0.") and success;
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success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During R_OP, sel_ra has to be 0.") and success;
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success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During R_OP, rf_wren has to be 1.") and success;
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success := bcheck(sel_rC, '1', "sel_rC", filename, counter, currenttime, " During R_OP, sel_rC has to be 1.") and success;
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success := bcheck(sel_b, '1', "sel_b", filename, counter, currenttime, " During R_OP, sel_b has to be 1.") and success;
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when RI_OP =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During RI_OP, write has to be 0.") and success;
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success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During RI_OP, pc_en has to be 0.") and success;
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success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During RI_OP, ir_en has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During RI_OP, branch_op has to be 0.") and success;
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success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During RI_OP, sel_mem has to be 0.") and success;
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success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During RI_OP, sel_pc has to be 0.") and success;
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success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During RI_OP, sel_b has to be 0.") and success;
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success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During RI_OP, sel_ra has to be 0.") and success;
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success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During RI_OP, rf_wren has to be 1.") and success;
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success := bcheck(sel_rC, '1', "sel_rC", filename, counter, currenttime, " During RI_OP, sel_rC has to be 1.") and success;
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when I_OP =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During I_OP, write has to be 0.") and success;
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success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During I_OP, pc_en has to be 0.") and success;
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success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During I_OP, ir_en has to be 0.") and success;
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success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During I_OP, branch_op has to be 0.") and success;
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success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During I_OP, sel_mem has to be 0.") and success;
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success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During I_OP, sel_pc has to be 0.") and success;
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success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During I_OP, sel_b has to be 0.") and success;
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success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During I_OP, sel_ra has to be 0.") and success;
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success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During I_OP, sel_rC has to be 0.") and success;
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success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During UI_OP, imm_signed has to be 1.") and success;
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success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During I_OP, rf_wren has to be 1.") and success;
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when UI_OP =>
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success := bcheck(write, '0', "write", filename, counter, currenttime, " During UI_OP, write has to be 0.") and success;
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success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During UI_OP, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During UI_OP, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During UI_OP, branch_op has to be 0.") and success;
|
||
|
|
success := bcheck(sel_mem, '0', "sel_mem", filename, counter, currenttime, " During UI_OP, sel_mem has to be 0.") and success;
|
||
|
|
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During UI_OP, sel_pc has to be 0.") and success;
|
||
|
|
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During UI_OP, sel_b has to be 0.") and success;
|
||
|
|
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During UI_OP, sel_ra has to be 0.") and success;
|
||
|
|
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During UI_OP, sel_rC has to be 0.") and success;
|
||
|
|
success := bcheck(imm_signed, '0', "imm_signed", filename, counter, currenttime, " During UI_OP, imm_signed has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During UI_OP, rf_wren has to be 1.") and success;
|
||
|
|
when LOAD1 =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During LOAD1, write has to be 0.") and success;
|
||
|
|
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During LOAD1, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During LOAD1, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During LOAD1, branch_op has to be 0.") and success;
|
||
|
|
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During LOAD1, sel_b has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During LOAD1, rf_wren has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(reads, '1', "read", filename, counter, currenttime, " During LOAD1, read has to be 1.") and success;
|
||
|
|
success := bcheck(sel_addr, '1', "sel_addr", filename, counter, currenttime, " During LOAD1, sel_addr has to be 1.") and success;
|
||
|
|
success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During LOAD1, imm_signed has to be 1.") and success;
|
||
|
|
when LOAD2 =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During LOAD2, write has to be 0.") and success;
|
||
|
|
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During LOAD2, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During LOAD2, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During LOAD2, branch_op has to be 0.") and success;
|
||
|
|
success := bcheck(sel_pc, '0', "sel_pc", filename, counter, currenttime, " During LOAD2, sel_pc has to be 0.") and success;
|
||
|
|
success := bcheck(sel_ra, '0', "sel_ra", filename, counter, currenttime, " During LOAD2, sel_ra has to be 0.") and success;
|
||
|
|
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During LOAD2, sel_rC has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(sel_mem, '1', "sel_mem", filename, counter, currenttime, " During LOAD2, sel_mem has to be 1.") and success;
|
||
|
|
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During LOAD2, rf_wren has to be 1.") and success;
|
||
|
|
when STORE =>
|
||
|
|
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During STORE, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During STORE, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During STORE, branch_op has to be 0.") and success;
|
||
|
|
success := bcheck(sel_b, '0', "sel_b", filename, counter, currenttime, " During STORE, sel_b has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During STORE, rf_wren has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(sel_addr, '1', "sel_addr", filename, counter, currenttime, " During STORE, sel_addr has to be 1.") and success;
|
||
|
|
success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During STORE, imm_signed has to be 1.") and success;
|
||
|
|
success := bcheck(write, '1', "write", filename, counter, currenttime, " During STORE, write has to be 1.") and success;
|
||
|
|
when BRANCH =>
|
||
|
|
if (unsigned(op) /= 6) then
|
||
|
|
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During BRANCH, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
|
||
|
|
end if;
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During BRANCH, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During BRANCH, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During BRANCH, rf_wren has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(branch_op, '1', "branch_op", filename, counter, currenttime, " During BRANCH, branch_op has to be 1.") and success;
|
||
|
|
--success := bcheck(imm_signed, '1', "imm_signed", filename, counter, currenttime, " During BRANCH, imm_signed has to be 1.") and success;
|
||
|
|
success := bcheck(sel_b, '1', "sel_b", filename, counter, currenttime, " During BRANCH, sel_b has to be 1.") and success;
|
||
|
|
success := bcheck(pc_add_imm, '1', "pc_add_imm", filename, counter, currenttime, " During BRANCH, pc_add_imm has to be 1.") and success;
|
||
|
|
when CALL =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During CALL, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During CALL, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During CALL, pc_add_imm has to be 0.") and success;
|
||
|
|
success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " During CALL, pc_sel_a has to be 0.") and success;
|
||
|
|
success := bcheck(sel_rC, '0', "sel_rC", filename, counter, currenttime, " During CALL, sel_rC has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(pc_sel_imm, '1', "pc_sel_imm", filename, counter, currenttime, " During CALL, pc_sel_imm has to be 1.") and success;
|
||
|
|
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During CALL, rf_wren has to be 1.") and success;
|
||
|
|
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During CALL, pc_en has to be 1.") and success;
|
||
|
|
success := bcheck(sel_pc, '1', "sel_pc", filename, counter, currenttime, " During CALL, sel_pc has to be 1.") and success;
|
||
|
|
success := bcheck(sel_ra, '1', "sel_ra", filename, counter, currenttime, " During CALL, sel_ra has to be 1.") and success;
|
||
|
|
when CALLR =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During CALLR, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During CALLR, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During CALLR, pc_add_imm has to be 0.") and success;
|
||
|
|
success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " During CALLR, pc_sel_imm has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(pc_sel_a, '1', "pc_sel_a", filename, counter, currenttime, " During CALLR, pc_sel_a has to be 1.") and success;
|
||
|
|
success := bcheck(rf_wren, '1', "rf_wren", filename, counter, currenttime, " During CALLR, rf_wren has to be 1.") and success;
|
||
|
|
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During CALLR, pc_en has to be 1.") and success;
|
||
|
|
success := bcheck(sel_pc, '1', "sel_pc", filename, counter, currenttime, " During CALLR, sel_pc has to be 1.") and success;
|
||
|
|
success := bcheck(sel_rC or sel_ra, '1', "sel_rC", filename, counter, currenttime, " During CALLR, sel_rC or sel_ra has to be 1.") and success;
|
||
|
|
when JMP =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During JMP, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During JMP, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During JMP, pc_add_imm has to be 0.") and success;
|
||
|
|
success := bcheck(pc_sel_imm, '0', "pc_sel_imm", filename, counter, currenttime, " During JMP, pc_sel_imm has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During JMP, rf_wren has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(pc_sel_a, '1', "pc_sel_a", filename, counter, currenttime, " During JMP, pc_sel_a has to be 1.") and success;
|
||
|
|
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During JMP, pc_en has to be 1.") and success;
|
||
|
|
when BREAK =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During BREAK, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During BREAK, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During BREAK, rf_wren has to be 0.") and success;
|
||
|
|
success := bcheck(pc_en, '0', "pc_en", filename, counter, currenttime, " During BREAK, pc_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During BREAK, branch_op has to be 0.") and success;
|
||
|
|
when JMPI =>
|
||
|
|
success := bcheck(write, '0', "write", filename, counter, currenttime, " During JMPI, write has to be 0.") and success;
|
||
|
|
success := bcheck(ir_en, '0', "ir_en", filename, counter, currenttime, " During JMPI, ir_en has to be 0.") and success;
|
||
|
|
success := bcheck(branch_op, '0', "branch_op", filename, counter, currenttime, " During JMPI, branch_op has to be 0.") and success;
|
||
|
|
success := bcheck(pc_add_imm, '0', "pc_add_imm", filename, counter, currenttime, " During JMPI, pc_add_imm has to be 0.") and success;
|
||
|
|
success := bcheck(pc_sel_a, '0', "pc_sel_a", filename, counter, currenttime, " During JMPI, pc_sel_a has to be 0.") and success;
|
||
|
|
success := bcheck(rf_wren, '0', "rf_wren", filename, counter, currenttime, " During JMPI, rf_wren has to be 0.") and success;
|
||
|
|
|
||
|
|
success := bcheck(pc_sel_imm, '1', "pc_sel_imm", filename, counter, currenttime, " During JMPI, pc_sel_imm has to be 1.") and success;
|
||
|
|
success := bcheck(pc_en, '1', "pc_en", filename, counter, currenttime, " During JMPI, pc_en has to be 1.") and success;
|
||
|
|
when others =>
|
||
|
|
end case;
|
||
|
|
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process(reset_n, clk)
|
||
|
|
begin
|
||
|
|
if (reset_n = '0') then
|
||
|
|
pc_counter <= 0;
|
||
|
|
elsif (rising_edge(clk)) then
|
||
|
|
sel_addr_reg <= sel_addr;
|
||
|
|
reg_read <= reads;
|
||
|
|
if (pc_en = '1' and (state < DECODE)) then
|
||
|
|
pc_counter <= pc_counter + 1;
|
||
|
|
elsif (state >= DECODE) then
|
||
|
|
pc_counter <= 0;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process
|
||
|
|
begin
|
||
|
|
if (finished) then
|
||
|
|
wait;
|
||
|
|
else
|
||
|
|
clk <= not clk;
|
||
|
|
wait for CLK_PERIOD / 2;
|
||
|
|
currenttime <= currenttime + CLK_PERIOD / 2;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
end testbench;
|