20 lines
399 B
VHDL
20 lines
399 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity extend is
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port(
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imm16 : in std_logic_vector(15 downto 0);
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signed : in std_logic;
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imm32 : out std_logic_vector(31 downto 0)
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);
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end extend;
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architecture synth of extend is
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begin
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imm32 <= (15 downto 0 => '0') & imm16 when signed = '0' else
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(15 downto 0 => imm16(15)) & imm16(15 downto 0);
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end synth;
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