36 lines
1006 B
VHDL
36 lines
1006 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity ClkGen is
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generic (
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F_OUT : natural; -- Hz
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F_CLK : natural -- Hz
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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clk_o : out std_logic;
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en : in std_logic
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);
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end ClkGen;
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architecture Behavioral of ClkGen is
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constant CNT_MAX : integer := integer(floor(real(F_CLK) / real(F_OUT))) - 1;
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signal counter_reg, counter_next: integer range CNT_MAX downto 0;
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begin
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counter_next <= CNT_MAX when counter_reg = 0 else counter_reg - 1;
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process(clk, rst_n) begin
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if rising_edge(clk) then
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if rst_n = '0' then
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counter_reg <= CNT_MAX;
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else
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if en = '1' then
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counter_reg <= counter_next;
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end if;
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end if;
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end if;
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end process;
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clk_o <= '1' when counter_reg = 0 and en = '1' else '0';
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end Behavioral; -- Behavioral
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