82 lines
2.3 KiB
VHDL
82 lines
2.3 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity buttons is
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port(
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-- bus interface
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clk : in std_logic;
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reset_n : in std_logic;
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cs : in std_logic;
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read : in std_logic;
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write : in std_logic;
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address : in std_logic;
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wrdata : in std_logic_vector(31 downto 0);
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buttons : in std_logic_vector(4 downto 0);
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-- irq : out std_logic;
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rddata : out std_logic_vector(31 downto 0)
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);
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end buttons;
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architecture synth of buttons is
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constant REG_DATA : std_logic := '0';
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constant REG_EDGE : std_logic := '1';
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signal address_reg : std_logic;
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signal read_reg : std_logic;
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signal buttons_reg : std_logic_vector(4 downto 0);
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signal edges : std_logic_vector(4 downto 0);
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begin
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--irq <= '0' when unsigned(edges) = 0 else '1';
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-- address_reg & button_reg
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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address_reg <= '0';
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read_reg <= '0';
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buttons_reg <= (others => '1');
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elsif (rising_edge(clk)) then
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address_reg <= address;
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read_reg <= read and cs;
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buttons_reg <= buttons;
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end if;
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end process;
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-- read
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process(read_reg, address_reg, edges, buttons)
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begin
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rddata <= (others => 'Z');
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if (read_reg = '1') then
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rddata <= (others => '0');
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case address_reg is
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when REG_DATA =>
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rddata(4 downto 0) <= buttons;
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when REG_EDGE =>
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rddata(4 downto 0) <= edges;
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when others =>
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end case;
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end if;
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end process;
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-- edges
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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edges <= (others => '0');
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elsif (rising_edge(clk)) then
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-- edge detection
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edges <= edges or (not buttons and buttons_reg);
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-- clear edges
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if (cs = '1' and write = '1') then
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if (address = REG_EDGE) then
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edges <= (others => '0');
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end if;
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end if;
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end if;
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end process;
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end synth;
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