107 lines
3.6 KiB
VHDL
107 lines
3.6 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity LEDs is
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port(
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-- bus interface
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clk : in std_logic;
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reset_n : in std_logic;
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cs : in std_logic;
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read : in std_logic;
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write : in std_logic;
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address : in std_logic_vector(1 downto 0);
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rddata : out std_logic_vector(31 downto 0);
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wrdata : in std_logic_vector(31 downto 0);
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-- external output
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LEDs : out std_logic_vector(95 downto 0)
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);
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end LEDs;
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architecture synth of LEDs is
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constant REG_LED_0_31 : std_logic_vector(1 downto 0) := "00";
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constant REG_LED_32_63 : std_logic_vector(1 downto 0) := "01";
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constant REG_LED_64_95 : std_logic_vector(1 downto 0) := "10";
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constant REG_DUTY_CYCLE : std_logic_vector(1 downto 0) := "11";
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signal reg_read : std_logic;
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signal reg_address : std_logic_vector(1 downto 0);
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signal counter : std_logic_vector(7 downto 0);
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signal LEDs_reg : std_logic_vector(95 downto 0);
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signal LEDs_FPGA4U : std_logic_vector(95 downto 0);
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signal duty_cycle : std_logic_vector(7 downto 0);
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begin
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LEDs_FPGA4U <= LEDs_reg when counter < duty_cycle else (others => '0');
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-- On FPGA4U, LEDs were addressed by column, on GECKO by row and mirrored
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-- Therefore, we need to transpose the indices and flip the indeces along x
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process(LEDs_FPGA4U)
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variable LEDs_before_transpose: std_logic_vector(95 downto 0);
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begin
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for i in 0 to 95 loop
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LEDs_before_transpose(i / 8 + (i mod 8) * 12) := LEDs_FPGA4U(i);
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LEDs(i) <= LEDs_before_transpose((i / 12 + 1) * 12 - 1 - (i mod 12));
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end loop;
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end process;
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-- registers
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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reg_read <= '0';
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reg_address <= (others => '0');
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counter <= (others => '0');
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elsif (rising_edge(clk)) then
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reg_read <= cs and read;
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reg_address <= address;
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if address /= REG_DUTY_CYCLE then
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counter <= std_logic_vector(unsigned(counter) + 1);
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else
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counter <= (others => '0');
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end if;
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end if;
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end process;
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-- read
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process(reg_read, reg_address, LEDs_reg, duty_cycle)
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begin
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rddata <= (others => 'Z');
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if (reg_read = '1') then
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rddata <= (others => '0');
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case reg_address is
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when REG_LED_0_31 =>
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rddata <= LEDs_reg(31 downto 0);
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when REG_LED_32_63 =>
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rddata <= LEDs_reg(63 downto 32);
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when REG_LED_64_95 =>
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rddata <= LEDs_reg(95 downto 64);
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when REG_DUTY_CYCLE =>
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rddata(7 downto 0) <= duty_cycle;
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when others =>
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end case;
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end if;
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end process;
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-- write
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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LEDs_reg <= (others => '0');
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duty_cycle <= X"0F";
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elsif (rising_edge(clk)) then
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if (cs = '1' and write = '1') then
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case address is
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when REG_LED_0_31 => LEDs_reg(31 downto 0) <= wrdata;
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when REG_LED_32_63 => LEDs_reg(63 downto 32) <= wrdata;
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when REG_LED_64_95 => LEDs_reg(95 downto 64) <= wrdata;
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when REG_DUTY_CYCLE => duty_cycle <= wrdata(7 downto 0);
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when others => null;
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end case;
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end if;
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end if;
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end process;
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end synth;
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