36 lines
1.0 KiB
VHDL
36 lines
1.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity add_sub is
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port(
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a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(31 downto 0);
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sub_mode : in std_logic;
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carry : out std_logic;
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zero : out std_logic;
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r : out std_logic_vector(31 downto 0)
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);
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end add_sub;
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architecture synth of add_sub is
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signal bsub : std_logic_vector(31 downto 0);
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signal temp : unsigned(32 downto 0);
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signal addout : std_logic_vector(32 downto 0);
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signal tempr : std_logic_vector(31 downto 0);
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signal subvec : std_logic_vector(31 downto 0);
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begin
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subvec <= ((31 downto 1 => '0') & sub_mode);
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bsub <= b xor (31 downto 0 => sub_mode);
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temp <= unsigned('0' & a) + unsigned('0' & bsub)+ unsigned('0' & subvec);
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addout <= std_logic_vector(temp);
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tempr <= addout(31 downto 0);
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carry <= addout(32);
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zero <= '1' when unsigned(tempr) = 0 else '0';
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r <= tempr;
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end synth;
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