49 lines
961 B
VHDL
49 lines
961 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ROM is
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port(
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clk : in std_logic;
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cs : in std_logic;
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read : in std_logic;
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address : in std_logic_vector(9 downto 0);
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rddata : out std_logic_vector(31 downto 0)
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);
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end ROM;
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architecture synth of ROM is
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signal reg_read : std_logic;
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signal reg_data : std_logic_vector(31 downto 0);
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component ROM_Block
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port(
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address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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);
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end component;
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begin
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-- romblock
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romblock : ROM_Block port map(
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address => address,
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clock => clk,
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q => reg_data
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);
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-- registers
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process(clk)
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begin
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if (rising_edge(clk) and cs = '1' and read = '1') then
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rddata <= reg_data;
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end if;
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end process;
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end synth;
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