112 lines
3.2 KiB
VHDL
112 lines
3.2 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.check_functions.all;
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entity tb_IR is
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end;
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architecture testbench of tb_IR is
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signal finished : boolean := false;
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signal currenttime : time := 0 ns;
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component IR is
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port(
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clk : in std_logic;
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enable : in std_logic;
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D : in std_logic_vector(31 downto 0);
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Q : out std_logic_vector(31 downto 0)
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);
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end component;
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constant CLK_PERIOD : time := 5 ns;
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signal clk : std_logic := '0';
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signal enable : std_logic := '0';
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signal D : std_logic_vector(31 downto 0) := (others => '0');
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signal Q : std_logic_vector(31 downto 0);
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begin
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ir_0 : IR port map(
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clk => clk,
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enable => enable,
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D => D,
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Q => Q
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);
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check : process
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constant filename : string := "IR/report.txt";
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file text_report : text is out filename;
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variable line_output : line;
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file text_input : text is in "IR/in.txt";
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variable line_input : line;
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variable counter : integer := 0;
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variable success : boolean := true;
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variable valid : std_logic;
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variable Q_cmp : std_logic_vector(31 downto 0);
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variable SINGLE_BIT : std_logic;
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variable WORD : std_logic_vector(31 downto 0);
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begin
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line_input := new string'("");
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if (endfile(text_input)) then
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finished <= true;
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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if (success) then
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line_output := new string'("Simulation is successful");
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else
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line_output := new string'("Errors encountered during simulation. Refer to the report.txt file.");
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end if;
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writeline(output, line_output);
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line_output := new string'("===================================================================");
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writeline(output, line_output);
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wait;
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end if;
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counter := counter + 1;
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readline(text_input, line_input);
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if (line_input'length /= 0) then
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if (line_input(1) = '-') then -- Print message
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line_output := line_input;
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writeline(output, line_input);
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elsif (line_input(1) /= '#') then
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wait until clk = '1';
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read(line_input, SINGLE_BIT);
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enable <= SINGLE_BIT;
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hread(line_input, WORD);
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D <= WORD;
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wait until clk = '0';
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read(line_input, valid);
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hread(line_input, Q_cmp);
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if (valid = '1') then
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success := hcheck(Q, Q_cmp, "Q", filename, counter, currenttime, "") and success;
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end if;
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end if;
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end if;
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end process;
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process
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begin
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if (finished) then
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wait;
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else
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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currenttime <= currenttime + CLK_PERIOD / 2;
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end if;
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end process;
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end testbench;
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