135 lines
4.3 KiB
Tcl
135 lines
4.3 KiB
Tcl
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# TCL File Generated by Component Editor 18.1
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# Fri Oct 30 13:47:37 CET 2020
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# DO NOT MODIFY
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#
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# WS28XX "WS28XX" v1.0
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# 2020.10.30.13:47:37
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module WS28XX
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME WS28XX
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME WS28XX
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL WS28XX
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file WS28XX.vhd VHDL PATH WS28XX.vhd TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clock_sink
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set_interface_property avalon_slave associatedReset reset_sink
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave maximumPendingWriteTransactions 0
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set_interface_property avalon_slave readLatency 0
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave address address Input 2
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add_interface_port avalon_slave write write Input 1
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add_interface_port avalon_slave writedata writedata Input 32
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add_interface_port avalon_slave read read Input 1
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add_interface_port avalon_slave readdata readdata Output 32
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set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink nReset reset_n Input 1
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#
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# connection point ws_out_source
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#
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add_interface ws_out_source conduit end
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set_interface_property ws_out_source associatedClock clock_sink
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set_interface_property ws_out_source associatedReset ""
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set_interface_property ws_out_source ENABLED true
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set_interface_property ws_out_source EXPORT_OF ""
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set_interface_property ws_out_source PORT_NAME_MAP ""
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set_interface_property ws_out_source CMSIS_SVD_VARIABLES ""
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set_interface_property ws_out_source SVD_ADDRESS_GROUP ""
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add_interface_port ws_out_source lout new_signal Output 1
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