41 lines
2.4 KiB
Plaintext
41 lines
2.4 KiB
Plaintext
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------+
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; Quartus Prime QXP Design File ;
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+------------------+---------------------------------------------------------+
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; Field ; Value ;
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+------------------+---------------------------------------------------------+
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; Entity ; decoder ;
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; Case Sensitive ; ;
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; QXP Source ; decoder-decoder_0.qxp ;
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; Software Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
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; Date ; Mon Oct 16 17:05:41 2017 ;
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; Contents ; Netlist Only ;
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; Family ; EP4CE30F23C8 ;
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; Device ; CYCLONEIVE3_V1F484C8 ;
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+------------------+---------------------------------------------------------+
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+--------------------------------------------+
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; Boundary Ports ;
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+----------------+--------+------------------+
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; Port Name ; Type ; Default Value ;
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+----------------+--------+------------------+
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; address [15:0] ; input ; 0000000000000000 ;
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; cs_Buttons ; output ; 0 ;
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; cs_LEDS ; output ; 0 ;
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; cs_RAM ; output ; 0 ;
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; cs_ROM ; output ; 0 ;
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+----------------+--------+------------------+
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