278 lines
11 KiB
VHDL
278 lines
11 KiB
VHDL
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-- RGB LEDs x96 simple interface
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-- author: xavier.jimenez@epfl.ch
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-- file: rgb_led96.vhd
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-- A simple interface to control 96 rgb leds.
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-- Monochrome version: every LED will have the same color.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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package pack is
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function f_ceil_log2 (constant n : natural)
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return natural;
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end pack;
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package body pack is
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-- computes ceil(log2(N))
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function f_ceil_log2 (constant n : natural) return natural is
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variable n_v : natural;
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variable ret : natural;
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begin
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assert n > 0
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report "pack.f_ceil_log2(n): input n should be greater than 0."
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severity error;
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ret := 0;
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n_v := 2*n-1;
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while n_v > 1 loop
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ret := ret + 1;
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n_v := n_v / 2;
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end loop;
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return ret;
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end f_ceil_log2;
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end pack;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_arith.all;
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USE work.pack.all;
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entity rgb_led96 is
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generic (
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-- input clock frequency in Hz
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CLK_FREQ : natural := 50000000;
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-- desired frame rate in Hz
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FRAME_RATE : natural := 100;
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DEFAULT_COLOR : std_logic_vector(23 downto 0) := X"0000FF"
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);
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port (
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-- global
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clk : in std_logic;
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reset : in std_logic;
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-- LEDs
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LEDs : in std_logic_vector(95 downto 0);
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-- a global color, 8 bits per channel, red by default
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color : in std_logic_vector(23 downto 0) := DEFAULT_COLOR; --X"0000FF";
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-- RGB LEDS matrix
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LED_SelC_n : out std_logic_vector(11 downto 0);
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LED_Sel_R : out std_logic_vector(7 downto 0);
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LED_Sel_G : out std_logic_vector(7 downto 0);
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LED_Sel_B : out std_logic_vector(7 downto 0);
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LED_reset : out std_logic
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);
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end entity;
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-- Architecture Body
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architecture arch of rgb_led96 is
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constant C_ROWS : natural := 8;
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constant C_COLUMNS : natural := 12;
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constant C_PWM_BITS : natural := 15;
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-- time spent reseting a line (fixed to 1us)
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constant C_PERIOD_RST : natural := CLK_FREQ/1000000;
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-- maximum time period per line to satisfy frame rate
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constant C_MAX_PERIOD : natural := CLK_FREQ/FRAME_RATE/C_COLUMNS - 1;
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-- pwm cycle count during a display phase.
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-- We fix the pwm on 2**15 clock cycles and want a display phase aligned to it
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-- total line refresh is made of: 2 transitional cycles, a reset phase and the display phase.
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constant C_PWM_CYCLES : natural := (C_MAX_PERIOD-C_PERIOD_RST-2)/(2**C_PWM_BITS);
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-- display period
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constant C_DISPLAY_PERIOD : natural := (2**C_PWM_BITS)*C_PWM_CYCLES;
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-- we get the bitwidth of the period counter
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constant C_PERIOD_WIDTH : natural := f_ceil_log2(C_DISPLAY_PERIOD);
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type t_matrix is array(0 to 11) of std_logic_vector(7 downto 0);
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signal s_led_matrix : t_matrix;
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-- a register to store the pwm threshold for the one value and each channel
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signal reg_pwm_thres : std_logic_vector(3*16-1 downto 0);
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-- period counter
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signal reg_period_cnt : std_logic_vector(C_PERIOD_WIDTH-1 downto 0);
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-- current col index
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signal reg_col_cnt : std_logic_vector(3 downto 0);
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-- current col vector (single bit active on a 24-bit vector)
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signal reg_sel_col : std_logic_vector(11 downto 0);
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-- gamma 2.2 array to translate RGB to pwm duty cycles
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type t_array16 is array (0 to 255) of std_logic_vector(15 downto 0);
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signal gamma_table : t_array16 :=
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( X"0000", X"0001", X"0002", X"0003", X"0004", X"0005", X"0006", X"0007", X"0008", X"0009", X"000A", X"000B", X"000C", X"000D", X"000E", X"000F", X"0010"
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, X"0011", X"0012", X"0013", X"0014", X"0015", X"0016", X"0017", X"0018", X"0019", X"001B", X"001D", X"0020", X"0022", X"0025", X"0028", X"002B"
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, X"002E", X"0031", X"0034", X"0037", X"003B", X"003E", X"0042", X"0046", X"0049", X"004D", X"0052", X"0056", X"005A", X"005F", X"0063", X"0068"
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, X"006D", X"0072", X"0077", X"007C", X"0081", X"0087", X"008C", X"0092", X"0098", X"009E", X"00A4", X"00AA", X"00B0", X"00B6", X"00BD", X"00C4"
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, X"00CA", X"00D1", X"00D8", X"00E0", X"00E7", X"00EE", X"00F6", X"00FE", X"0105", X"010D", X"0115", X"011E", X"0126", X"012E", X"0137", X"0140"
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, X"0149", X"0152", X"015B", X"0164", X"016D", X"0177", X"0181", X"018A", X"0194", X"019E", X"01A8", X"01B3", X"01BD", X"01C8", X"01D3", X"01DD"
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, X"01E9", X"01F4", X"01FF", X"020A", X"0216", X"0222", X"022D", X"0239", X"0246", X"0252", X"025E", X"026B", X"0277", X"0284", X"0291", X"029E"
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, X"02AC", X"02B9", X"02C6", X"02D4", X"02E2", X"02F0", X"02FE", X"030C", X"031B", X"0329", X"0338", X"0346", X"0355", X"0365", X"0374", X"0383"
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, X"0393", X"03A2", X"03B2", X"03C2", X"03D2", X"03E2", X"03F3", X"0403", X"0414", X"0425", X"0436", X"0447", X"0458", X"046A", X"047B", X"048D"
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, X"049F", X"04B1", X"04C3", X"04D6", X"04E8", X"04FB", X"050D", X"0520", X"0533", X"0547", X"055A", X"056D", X"0581", X"0595", X"05A9", X"05BD"
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, X"05D1", X"05E6", X"05FA", X"060F", X"0624", X"0639", X"064E", X"0664", X"0679", X"068F", X"06A4", X"06BA", X"06D1", X"06E7", X"06FD", X"0714"
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, X"072A", X"0741", X"0758", X"0770", X"0787", X"079E", X"07B6", X"07CE", X"07E6", X"07FE", X"0816", X"082F", X"0847", X"0860", X"0879", X"0892"
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, X"08AB", X"08C5", X"08DE", X"08F8", X"0912", X"092C", X"0946", X"0960", X"097B", X"0995", X"09B0", X"09CB", X"09E6", X"0A01", X"0A1D", X"0A38"
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, X"0A54", X"0A70", X"0A8C", X"0AA8", X"0AC5", X"0AE1", X"0AFE", X"0B1B", X"0B38", X"0B55", X"0B73", X"0B90", X"0BAE", X"0BCC", X"0BEA", X"0C08"
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, X"0C26", X"0C45", X"0C63", X"0C82", X"0CA1", X"0CC0", X"0CDF", X"0CFF", X"0D1F", X"0D3E", X"0D5E", X"0D7E", X"0D9F", X"0DBF", X"0DE0", X"0E01"
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, X"0E22", X"0E43", X"0E64", X"0E85", X"0EA7", X"0EC9", X"0EEB", X"0F0D", X"0F2F", X"0F51", X"0F74", X"0F97", X"0FBA", X"0FDD", X"1000");
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signal s_gamma_addr : std_logic_vector(7 downto 0);
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signal reg_gamma_data : std_logic_vector(15 downto 0);
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-- FSM
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type t_state is (TRANS1, RST, TRANS2, DISPLAY);
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signal state, next_state : t_state;
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begin
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-- led matrix mapping
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g_matrix_i : for i in 0 to 11 generate
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s_led_matrix(i) <= LEDs((i+1)*8-1 downto i*8);
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end generate;
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-- col activation
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LED_SelC_n <= not reg_sel_col when state = DISPLAY else (others => '1');
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-- row activation
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process (reg_period_cnt, state, reg_pwm_thres, s_led_matrix, reg_col_cnt)
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variable v_pwm : std_logic_vector(C_PWM_BITS-1 downto 0);
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begin
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-- by default, each channel at 0
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LED_Sel_R <= (others=>'0');
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LED_Sel_G <= (others=>'0');
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LED_Sel_B <= (others=>'0');
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v_pwm := reg_period_cnt(C_PWM_BITS-1 downto 0);
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if (state = DISPLAY) then
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if (reg_pwm_thres(46 downto 32) > v_pwm) then
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LED_Sel_R <= s_led_matrix(conv_integer(reg_col_cnt));
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end if;
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-- green
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if (reg_pwm_thres(30 downto 16) > v_pwm) then
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LED_Sel_G <= s_led_matrix(conv_integer(reg_col_cnt));
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end if;
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-- blue
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if (reg_pwm_thres(14 downto 0) > v_pwm) then
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LED_Sel_B <= s_led_matrix(conv_integer(reg_col_cnt));
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end if;
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end if;
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end process;
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-- combinatorial gamma address
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process (color, state, reg_period_cnt)
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begin
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-- the address to the gamma table
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-- by default we point on the first channel
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s_gamma_addr <= color(7 downto 0); -- (blue)
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-- then during the first two cycle of the reset phase, we switch to the other two
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if (state = RST) then
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if (reg_period_cnt <= 1) then
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if (reg_period_cnt(0) = '0') then
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s_gamma_addr <= color(15 downto 8); -- (green)
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else
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s_gamma_addr <= color(23 downto 16); -- (red)
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end if;
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end if;
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end if;
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end process;
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-- loading the pwm threshold reference for the 1s during the reset state.
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process (clk) -- no need for reset
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begin
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if (rising_edge(clk)) then
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reg_gamma_data <= gamma_table(conv_integer(s_gamma_addr));
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-- the reg column
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if (state = RST) then
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if (reg_period_cnt <= 2) then
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-- for green and blue the value must be doubled
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case reg_period_cnt(1 downto 0) is
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when "00" | "01" =>
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-- (blue and green delayed by 1 cycle (reading gamma has 1-cycle latency))
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reg_pwm_thres <= reg_gamma_data(14 downto 0) & '0' & reg_pwm_thres(3*16-1 downto 16);
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when others =>
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reg_pwm_thres <= reg_gamma_data & reg_pwm_thres(3*16-1 downto 16);
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end case;
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end if;
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end if;
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end if;
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end process;
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-- registers and counters
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process (reset, clk)
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begin
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if (reset = '1') then
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state <= TRANS1;
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reg_period_cnt <= (others => '0');
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reg_col_cnt <= (others => '0');
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reg_sel_col <= (0 => '1', others => '0');
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elsif rising_edge(clk) then
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state <= next_state;
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-- period counter
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case state is
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when TRANS1 | TRANS2 =>
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reg_period_cnt <= (others => '0');
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when RST | DISPLAY =>
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reg_period_cnt <= reg_period_cnt + 1;
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when others =>
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end case;
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-- new column
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if (state = TRANS1) then
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-- we activate the next column
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reg_sel_col <= reg_sel_col(10 downto 0) & reg_sel_col(11);
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-- we update the column index after a reset, during trans2
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if (reg_col_cnt = 11) then
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reg_col_cnt <= (others => '0');
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else
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reg_col_cnt <= reg_col_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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-- Simple state machine to switch between reset and display periods.
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-- Between each transition we deactivate every signal for 1 cycle to
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-- ensure that the RGB_reset signal cannot be activated along with a
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-- column selection (shortcut)
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process (state, reg_period_cnt)
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begin
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LED_reset <= '0';
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next_state <= state;
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case state is
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when TRANS1 =>
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next_state <= RST;
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when RST =>
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LED_reset <= '1';
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if (reg_period_cnt = C_PERIOD_RST-1) then
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next_state <= TRANS2;
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end if;
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when TRANS2 =>
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next_state <= DISPLAY;
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when DISPLAY =>
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if (reg_period_cnt = C_DISPLAY_PERIOD-1) then
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next_state <= TRANS1;
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end if;
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when others =>
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end case;
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end process;
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end architecture;
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