23 lines
569 B
VHDL
23 lines
569 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity multiplexer is
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port(
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i0 : in std_logic_vector(31 downto 0);
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i1 : in std_logic_vector(31 downto 0);
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i2 : in std_logic_vector(31 downto 0);
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i3 : in std_logic_vector(31 downto 0);
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sel : in std_logic_vector(1 downto 0);
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o : out std_logic_vector(31 downto 0)
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);
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end multiplexer;
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architecture synth of multiplexer is
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begin
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o <= i0 when sel = "00" else
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i1 when sel = "01" else
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i2 when sel = "10" else
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i3 when sel = "11" else
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i0;
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end synth;
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