20 lines
476 B
VHDL
20 lines
476 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity logic_unit is
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port(
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a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(31 downto 0);
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op : in std_logic_vector(1 downto 0);
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r : out std_logic_vector(31 downto 0)
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);
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end logic_unit;
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architecture synth of logic_unit is
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begin
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r <= a nor b when op = "00" else
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a and b when op = "01" else
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a or b when op = "10" else
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a xnor b;
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end synth;
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