46 lines
973 B
VHDL
46 lines
973 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity decoder is
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port(
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address : in std_logic_vector(15 downto 0);
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cs_LEDS : out std_logic;
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cs_RAM : out std_logic;
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cs_ROM : out std_logic;
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cs_buttons : out std_logic
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);
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end decoder;
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architecture synth of decoder is
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begin
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process(address)
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begin
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if(address <= X"0FFC") then
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cs_ROM <='1';
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cs_RAM <= '0';
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cs_LEDS <= '0';
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cs_buttons <= '0';
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elsif(address <= X"1FFC") then
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cs_ROM <='0';
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cs_RAM <= '1';
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cs_LEDS <= '0';
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cs_buttons <= '0';
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elsif(address <= X"200C") then
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cs_ROM <='0';
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cs_RAM <= '0';
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cs_LEDS <= '1';
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cs_buttons <= '0';
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elsif(address >= x"2030" and address < x"2034") then
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cs_ROM <='0';
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cs_RAM <= '0';
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cs_LEDS <= '0';
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cs_buttons <= '1';
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else
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cs_ROM <='0';
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cs_RAM <= '0';
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cs_LEDS <= '0';
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cs_buttons <= '0';
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end if;
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end process;
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end synth;
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