26 lines
808 B
VHDL
26 lines
808 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity comparator is
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port(
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a_31 : in std_logic;
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b_31 : in std_logic;
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diff_31 : in std_logic;
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carry : in std_logic;
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zero : in std_logic;
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op : in std_logic_vector(2 downto 0);
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r : out std_logic
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);
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end comparator;
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architecture synth of comparator is
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begin
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r <= ((a_31 and (not(b_31))) or ((a_31 xnor b_31) and (diff_31 or zero))) when op = "001" else
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((not(a_31) and b_31) or ((a_31 xnor b_31) and (not(diff_31 or zero)))) when op = "010" else
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not(zero) when op = "011" else
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(not(carry) or zero) when op = "101" else
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(carry and not(zero)) when op = "110" else
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zero;
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end synth;
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