190 lines
129 KiB
Plaintext
190 lines
129 KiB
Plaintext
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{ "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/controller.vhd " "Source file: E:/cs208/vhdl/controller.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374911977 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/decoder.vhd " "Source file: E:/cs208/vhdl/decoder.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374911977 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/LEDs.vhd " "Source file: E:/cs208/vhdl/LEDs.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374911977 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/PC.vhd " "Source file: E:/cs208/vhdl/PC.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374911977 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/register_file.vhd " "Source file: E:/cs208/vhdl/register_file.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374911977 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Design Software" 0 -1 1540374911977 ""}
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{ "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/controller.vhd " "Source file: E:/cs208/vhdl/controller.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912602 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/decoder.vhd " "Source file: E:/cs208/vhdl/decoder.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912602 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/LEDs.vhd " "Source file: E:/cs208/vhdl/LEDs.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912602 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/PC.vhd " "Source file: E:/cs208/vhdl/PC.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912602 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/register_file.vhd " "Source file: E:/cs208/vhdl/register_file.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912602 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Design Software" 0 -1 1540374912602 ""}
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{ "Info" "IFLOW_SR_FILE_CHANGED_BASE" "" "Detected changes in source files." { { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/controller.vhd " "Source file: E:/cs208/vhdl/controller.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912727 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/decoder.vhd " "Source file: E:/cs208/vhdl/decoder.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912727 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/LEDs.vhd " "Source file: E:/cs208/vhdl/LEDs.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912727 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/PC.vhd " "Source file: E:/cs208/vhdl/PC.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912727 ""} { "Info" "IFLOW_SR_FILE_CHANGED" "E:/cs208/vhdl/register_file.vhd " "Source file: E:/cs208/vhdl/register_file.vhd has changed." { } { } 0 293027 "Source file: %1!s! has changed." 0 0 "Design Software" 0 -1 1540374912727 ""} } { } 0 293032 "Detected changes in source files." 0 0 "Design Software" 0 -1 1540374912727 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1540374915211 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540374915211 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 11:55:15 2018 " "Processing started: Wed Oct 24 11:55:15 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540374915211 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374915211 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO " "Command: quartus_map --read_settings_files=on --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374915211 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1540374916586 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1540374916586 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gecko.bdf 1 1 " "Found 1 design units, including 1 entities, in source file gecko.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GECKO " "Found entity 1: GECKO" { } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374929476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374929476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.bdf 1 1 " "Found 1 design units, including 1 entities, in source file alu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Found entity 1: ALU" { } { { "ALU.bdf" "" { Schematic "E:/cs208/quartus/ALU.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374929476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374929476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.bdf 1 1 " "Found 1 design units, including 1 entities, in source file cpu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Found entity 1: CPU" { } { { "CPU.bdf" "" { Schematic "E:/cs208/quartus/CPU.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374929476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374929476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/add_sub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/add_sub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_sub-synth " "Found design unit 1: add_sub-synth" { } { { "../vhdl/add_sub.vhd" "" { Text "E:/cs208/vhdl/add_sub.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930070 ""} { "Info" "ISGN_ENTITY_NAME" "1 add_sub " "Found entity 1: add_sub" { } { { "../vhdl/add_sub.vhd" "" { Text "E:/cs208/vhdl/add_sub.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930070 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930070 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/buttons.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/buttons.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buttons-synth " "Found design unit 1: buttons-synth" { } { { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930132 ""} { "Info" "ISGN_ENTITY_NAME" "1 buttons " "Found entity 1: buttons" { } { { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930132 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930132 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/comparator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/comparator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 comparator-synth " "Found design unit 1: comparator-synth" { } { { "../vhdl/comparator.vhd" "" { Text "E:/cs208/vhdl/comparator.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930148 ""} { "Info" "ISGN_ENTITY_NAME" "1 comparator " "Found entity 1: comparator" { } { { "../vhdl/comparator.vhd" "" { Text "E:/cs208/vhdl/comparator.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930148 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930148 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-synth " "Found design unit 1: controller-synth" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 39 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930148 ""} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Found entity 1: controller" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930148 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930148 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/decoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-synth " "Found design unit 1: decoder-synth" { } { { "../vhdl/decoder.vhd" "" { Text "E:/cs208/vhdl/decoder.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930164 ""} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "../vhdl/decoder.vhd" "" { Text "E:/cs208/vhdl/decoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930164 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930164 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/extend.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/extend.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 extend-synth " "Found design unit 1: extend-synth" { } { { "../vhdl/extend.vhd" "" { Text "E:/cs208/vhdl/extend.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930164 ""} { "Info" "ISGN_ENTITY_NAME" "1 extend " "Found entity 1: extend" { } { { "../vhdl/extend.vhd" "" { Text "E:/cs208/vhdl/extend.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930164 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930164 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/ir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/ir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IR-synth " "Found design unit 1: IR-synth" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930304 ""} { "Info" "ISGN_ENTITY_NAME" "1 IR " "Found entity 1: IR" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930304 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930304 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/leds.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/leds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LEDs-synth " "Found design unit 1: LEDs-synth" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930304 ""} { "Info" "ISGN_ENTITY_NAME" "1 LEDs " "Found entity 1: LEDs" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930304 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930304 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/logic_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/logic_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 logic_unit-synth " "Found design unit 1: logic_unit-synth" { } { { "../vhdl/logic_unit.vhd" "" { Text "E:/cs208/vhdl/logic_unit.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930320 ""} { "Info" "ISGN_ENTITY_NAME" "1 logic_unit " "Found entity 1: logic_unit" { } { { "../vhdl/logic_unit.vhd" "" { Text "E:/cs208/vhdl/logic_unit.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930320 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930320 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/multiplexer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/multiplexer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 multiplexer-synth " "Found design unit 1: multiplexer-synth" { } { { "../vhdl/multiplexer.vhd" "" { Text "E:/cs208/vhdl/multiplexer.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930320 ""} { "Info" "ISGN_ENTITY_NAME" "1 multiplexer " "Found entity 1: multiplexer" { } { { "../vhdl/multiplexer.vhd" "" { Text "E:/cs208/vhdl/multiplexer.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930320 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930320 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x5.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x5-synth " "Found design unit 1: mux2x5-synth" { } { { "../vhdl/mux2x5.vhd" "" { Text "E:/cs208/vhdl/mux2x5.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930336 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x5 " "Found entity 1: mux2x5" { } { { "../vhdl/mux2x5.vhd" "" { Text "E:/cs208/vhdl/mux2x5.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930336 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x16.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x16-synth " "Found design unit 1: mux2x16-synth" { } { { "../vhdl/mux2x16.vhd" "" { Text "E:/cs208/vhdl/mux2x16.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930461 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x16 " "Found entity 1: mux2x16" { } { { "../vhdl/mux2x16.vhd" "" { Text "E:/cs208/vhdl/mux2x16.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930461 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/mux2x32.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/mux2x32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux2x32-synth " "Found design unit 1: mux2x32-synth" { } { { "../vhdl/mux2x32.vhd" "" { Text "E:/cs208/vhdl/mux2x32.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930461 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux2x32 " "Found entity 1: mux2x32" { } { { "../vhdl/mux2x32.vhd" "" { Text "E:/cs208/vhdl/mux2x32.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930461 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/pc.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/pc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PC-synth " "Found design unit 1: PC-synth" { } { { "../vhdl/PC.vhd" "" { Text "E:/cs208/vhdl/PC.vhd" 19 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930476 ""} { "Info" "ISGN_ENTITY_NAME" "1 PC " "Found entity 1: PC" { } { { "../vhdl/PC.vhd" "" { Text "E:/cs208/vhdl/PC.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/ram.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM-synth " "Found design unit 1: RAM-synth" { } { { "../vhdl/RAM.vhd" "" { Text "E:/cs208/vhdl/RAM.vhd" 16 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930476 ""} { "Info" "ISGN_ENTITY_NAME" "1 RAM " "Found entity 1: RAM" { } { { "../vhdl/RAM.vhd" "" { Text "E:/cs208/vhdl/RAM.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930476 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/register_file.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/register_file.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 register_file-synth " "Found design unit 1: register_file-synth" { } { { "../vhdl/register_file.vhd" "" { Text "E:/cs208/vhdl/register_file.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930492 ""} { "Info" "ISGN_ENTITY_NAME" "1 register_file " "Found entity 1: register_file" { } { { "../vhdl/register_file.vhd" "" { Text "E:/cs208/vhdl/register_file.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930492 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/rom.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-synth " "Found design unit 1: ROM-synth" { } { { "../vhdl/ROM.vhd" "" { Text "E:/cs208/vhdl/ROM.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930492 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" { } { { "../vhdl/ROM.vhd" "" { Text "E:/cs208/vhdl/ROM.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930492 ""}
|
||
|
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/rom_block.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/rom_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_block-SYN " "Found design unit 1: rom_block-SYN" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 52 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930570 ""} { "Info" "ISGN_ENTITY_NAME" "1 ROM_Block " "Found entity 1: ROM_Block" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930570 ""}
|
||
|
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/cs208/vhdl/shift_unit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /cs208/vhdl/shift_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_unit-synth " "Found design unit 1: shift_unit-synth" { } { { "../vhdl/shift_unit.vhd" "" { Text "E:/cs208/vhdl/shift_unit.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930586 ""} { "Info" "ISGN_ENTITY_NAME" "1 shift_unit " "Found entity 1: shift_unit" { } { { "../vhdl/shift_unit.vhd" "" { Text "E:/cs208/vhdl/shift_unit.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374930586 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374930586 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_TOP" "GECKO " "Elaborating entity \"GECKO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1540374931117 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LEDs LEDs:LEDs_0 " "Elaborating entity \"LEDs\" for hierarchy \"LEDs:LEDs_0\"" { } { { "GECKO.bdf" "LEDs_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 160 1040 1176 336 "LEDs_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931132 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:decoder_0 " "Elaborating entity \"decoder\" for hierarchy \"decoder:decoder_0\"" { } { { "GECKO.bdf" "decoder_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 96 408 544 232 "decoder_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931226 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CPU CPU:inst " "Elaborating entity \"CPU\" for hierarchy \"CPU:inst\"" { } { { "GECKO.bdf" "inst" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 328 168 376 456 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931242 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller CPU:inst\|controller:controller_0 " "Elaborating entity \"controller\" for hierarchy \"CPU:inst\|controller:controller_0\"" { } { { "CPU.bdf" "controller_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { -208 240 400 112 "controller_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931257 ""}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.RI_OP controller.vhd(58) " "Inferred latch for \"s_next.RI_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931257 "|GECKO|CPU:inst|controller:controller_0"}
|
||
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.UI_OP controller.vhd(58) " "Inferred latch for \"s_next.UI_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.JMPI controller.vhd(58) " "Inferred latch for \"s_next.JMPI\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.JMP controller.vhd(58) " "Inferred latch for \"s_next.JMP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.CALLR controller.vhd(58) " "Inferred latch for \"s_next.CALLR\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.CALL controller.vhd(58) " "Inferred latch for \"s_next.CALL\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.BRANCH controller.vhd(58) " "Inferred latch for \"s_next.BRANCH\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.LOAD2 controller.vhd(58) " "Inferred latch for \"s_next.LOAD2\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.I_OP controller.vhd(58) " "Inferred latch for \"s_next.I_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.LOAD1 controller.vhd(58) " "Inferred latch for \"s_next.LOAD1\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.BREAK controller.vhd(58) " "Inferred latch for \"s_next.BREAK\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.STORE controller.vhd(58) " "Inferred latch for \"s_next.STORE\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.R_OP controller.vhd(58) " "Inferred latch for \"s_next.R_OP\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.DECODE controller.vhd(58) " "Inferred latch for \"s_next.DECODE\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.FETCH2 controller.vhd(58) " "Inferred latch for \"s_next.FETCH2\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "s_next.FETCH1 controller.vhd(58) " "Inferred latch for \"s_next.FETCH1\" at controller.vhd(58)" { } { { "../vhdl/controller.vhd" "" { Text "E:/cs208/vhdl/controller.vhd" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374931336 "|GECKO|CPU:inst|controller:controller_0"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IR CPU:inst\|IR:IR_0 " "Elaborating entity \"IR\" for hierarchy \"CPU:inst\|IR:IR_0\"" { } { { "CPU.bdf" "IR_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 88 24 136 184 "IR_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931429 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x16 CPU:inst\|mux2x16:mux_addr " "Elaborating entity \"mux2x16\" for hierarchy \"CPU:inst\|mux2x16:mux_addr\"" { } { { "CPU.bdf" "mux_addr" { Schematic "E:/cs208/quartus/CPU.bdf" { { -40 1088 1144 56 "mux_addr" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931429 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PC CPU:inst\|PC:PC_0 " "Elaborating entity \"PC\" for hierarchy \"CPU:inst\|PC:PC_0\"" { } { { "CPU.bdf" "PC_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { -184 808 968 -8 "PC_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931492 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU CPU:inst\|ALU:alu_0 " "Elaborating entity \"ALU\" for hierarchy \"CPU:inst\|ALU:alu_0\"" { } { { "CPU.bdf" "alu_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 120 904 992 232 "alu_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931585 ""}
|
||
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multiplexer CPU:inst\|ALU:alu_0\|multiplexer:multiplexer_0 " "Elaborating entity \"multiplexer\" for hierarchy \"CPU:inst\|ALU:alu_0\|multiplexer:multiplexer_0\"" { } { { "ALU.bdf" "multiplexer_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -168 544 648 -32 "multiplexer_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931585 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub CPU:inst\|ALU:alu_0\|add_sub:add_sub_0 " "Elaborating entity \"add_sub\" for hierarchy \"CPU:inst\|ALU:alu_0\|add_sub:add_sub_0\"" { } { { "ALU.bdf" "add_sub_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -168 160 416 -72 "add_sub_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931601 ""}
|
||
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comparator CPU:inst\|ALU:alu_0\|comparator:comparator_0 " "Elaborating entity \"comparator\" for hierarchy \"CPU:inst\|ALU:alu_0\|comparator:comparator_0\"" { } { { "ALU.bdf" "comparator_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { -40 160 416 64 "comparator_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931601 ""}
|
||
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "logic_unit CPU:inst\|ALU:alu_0\|logic_unit:logic_unit_0 " "Elaborating entity \"logic_unit\" for hierarchy \"CPU:inst\|ALU:alu_0\|logic_unit:logic_unit_0\"" { } { { "ALU.bdf" "logic_unit_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { 80 160 416 176 "logic_unit_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931601 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_unit CPU:inst\|ALU:alu_0\|shift_unit:shift_unit_0 " "Elaborating entity \"shift_unit\" for hierarchy \"CPU:inst\|ALU:alu_0\|shift_unit:shift_unit_0\"" { } { { "ALU.bdf" "shift_unit_0" { Schematic "E:/cs208/quartus/ALU.bdf" { { 192 160 416 288 "shift_unit_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931617 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file CPU:inst\|register_file:register_file_0 " "Elaborating entity \"register_file\" for hierarchy \"CPU:inst\|register_file:register_file_0\"" { } { { "CPU.bdf" "register_file_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 120 600 752 264 "register_file_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931632 ""}
|
||
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x5 CPU:inst\|mux2x5:mux_aw " "Elaborating entity \"mux2x5\" for hierarchy \"CPU:inst\|mux2x5:mux_aw\"" { } { { "CPU.bdf" "mux_aw" { Schematic "E:/cs208/quartus/CPU.bdf" { { 152 440 496 248 "mux_aw" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931773 ""}
|
||
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2x32 CPU:inst\|mux2x32:mux_data " "Elaborating entity \"mux2x32\" for hierarchy \"CPU:inst\|mux2x32:mux_data\"" { } { { "CPU.bdf" "mux_data" { Schematic "E:/cs208/quartus/CPU.bdf" { { 144 1136 1192 240 "mux_data" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931835 ""}
|
||
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "extend CPU:inst\|extend:extend_0 " "Elaborating entity \"extend\" for hierarchy \"CPU:inst\|extend:extend_0\"" { } { { "CPU.bdf" "extend_0" { Schematic "E:/cs208/quartus/CPU.bdf" { { 24 568 752 104 "extend_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931898 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:ROM_0 " "Elaborating entity \"ROM\" for hierarchy \"ROM:ROM_0\"" { } { { "GECKO.bdf" "ROM_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 176 616 736 296 "ROM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931960 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM_Block ROM:ROM_0\|ROM_Block:romblock " "Elaborating entity \"ROM_Block\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\"" { } { { "../vhdl/ROM.vhd" "romblock" { Text "E:/cs208/vhdl/ROM.vhd" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374931976 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "altsyncram_component" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374932257 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\"" { } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374932320 ""}
|
||
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ../quartus/ROM.hex " "Parameter \"init_file\" = \"../quartus/ROM.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374932320 ""} } { { "../vhdl/ROM_Block.vhd" "" { Text "E:/cs208/vhdl/ROM_Block.vhd" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1540374932320 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rna1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_rna1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rna1 " "Found entity 1: altsyncram_rna1" { } { { "db/altsyncram_rna1.tdf" "" { Text "E:/cs208/quartus/db/altsyncram_rna1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374932445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374932445 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rna1 ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated " "Elaborating entity \"altsyncram_rna1\" for hierarchy \"ROM:ROM_0\|ROM_Block:romblock\|altsyncram:altsyncram_component\|altsyncram_rna1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga_lite/18.0/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374932445 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM RAM:RAM_0 " "Elaborating entity \"RAM\" for hierarchy \"RAM:RAM_0\"" { } { { "GECKO.bdf" "RAM_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 176 816 960 296 "RAM_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374932757 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buttons buttons:buttons_0 " "Elaborating entity \"buttons\" for hierarchy \"buttons:buttons_0\"" { } { { "GECKO.bdf" "buttons_0" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 160 1248 1384 336 "buttons_0" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374932789 ""}
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{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[31\]\" " "Converted tri-state node \"rddata\[31\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[30\]\" " "Converted tri-state node \"rddata\[30\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[29\]\" " "Converted tri-state node \"rddata\[29\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[28\]\" " "Converted tri-state node \"rddata\[28\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[27\]\" " "Converted tri-state node \"rddata\[27\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[26\]\" " "Converted tri-state node \"rddata\[26\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[25\]\" " "Converted tri-state node \"rddata\[25\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[24\]\" " "Converted tri-state node \"rddata\[24\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[23\]\" " "Converted tri-state node \"rddata\[23\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[22\]\" " "Converted tri-state node \"rddata\[22\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[21\]\" " "Converted tri-state node \"rddata\[21\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[20\]\" " "Converted tri-state node \"rddata\[20\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"rddata\[19\]\" " "Converted tri-state node \"rddata\[19\]\" into a selector" { } { { "../vhdl/IR.vhd" "" { Text "E:/cs208/vhdl/IR.vhd" 21 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Design Software" 0 -1 1540374933523 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR"
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{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "RAM:RAM_0\|reg_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"RAM:RAM_0\|reg_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Parameter OPERATION_MODE set to SINGLE_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Parameter WIDTHAD_A set to 10" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Parameter NUMWORDS_A set to 1024" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/GECKO.ram0_RAM_15119.hdl.mif " "Parameter INIT_FILE set to db/GECKO.ram0_RAM_15119.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1540374936632 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1540374936632 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1540374936632 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "RAM:RAM_0\|altsyncram:reg_rtl_0 " "Elaborated megafunction instantiation \"RAM:RAM_0\|altsyncram:reg_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374936898 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "RAM:RAM_0\|altsyncram:reg_rtl_0 " "Instantiated megafunction \"RAM:RAM_0\|altsyncram:reg_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 10 " "Parameter \"WIDTHAD_A\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 1024 " "Parameter \"NUMWORDS_A\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/GECKO.ram0_RAM_15119.hdl.mif " "Parameter \"INIT_FILE\" = \"db/GECKO.ram0_RAM_15119.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1540374936898 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1540374936898 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u781.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_u781.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u781 " "Found entity 1: altsyncram_u781" { } { { "db/altsyncram_u781.tdf" "" { Text "E:/cs208/quartus/db/altsyncram_u781.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1540374937007 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374937007 ""}
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{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../vhdl/LEDs.vhd" "" { Text "E:/cs208/vhdl/LEDs.vhd" 90 -1 0 } } { "../vhdl/buttons.vhd" "" { Text "E:/cs208/vhdl/buttons.vhd" 37 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1540374938319 ""}
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{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1540374938319 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1540374940585 ""}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "17 " "17 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1540374944694 ""}
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||
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1540374945382 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1540374945382 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "3816 " "Implemented 3816 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1540374945850 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1540374945850 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3650 " "Implemented 3650 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1540374945850 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1540374945850 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1540374945850 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 34 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540374945960 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 11:55:45 2018 " "Processing ended: Wed Oct 24 11:55:45 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540374945960 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540374945960 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540374945960 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1540374945960 ""}
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||
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1540374948210 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540374948210 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 11:55:47 2018 " "Processing started: Wed Oct 24 11:55:47 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540374948210 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1540374948210 ""}
|
||
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GECKO -c GECKO " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1540374948210 ""}
|
||
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{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1540374948850 ""}
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||
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{ "Info" "0" "" "Project = GECKO" { } { } 0 0 "Project = GECKO" 0 0 "Fitter" 0 0 1540374948850 ""}
|
||
|
|
{ "Info" "0" "" "Revision = GECKO" { } { } 0 0 "Revision = GECKO" 0 0 "Fitter" 0 0 1540374948850 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1540374949413 ""}
|
||
|
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1540374949538 ""}
|
||
|
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GECKO EP4CE30F23C8 " "Selected device EP4CE30F23C8 for design \"GECKO\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1540374949569 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1540374949647 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1540374949647 ""}
|
||
|
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1540374950006 ""}
|
||
|
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1540374950022 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F23C8 " "Device EP4CE15F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540374951006 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F23C8 " "Device EP4CE40F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540374951006 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F23C8 " "Device EP4CE55F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540374951006 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F23C8 " "Device EP4CE75F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540374951006 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F23C8 " "Device EP4CE115F23C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1540374951006 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1540374951006 ""}
|
||
|
|
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5425 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540374951022 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5427 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540374951022 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5429 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540374951022 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5431 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1540374951022 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1540374951022 ""}
|
||
|
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1540374951116 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1540374951319 ""}
|
||
|
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "The Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1540374952350 ""}
|
||
|
|
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1540374952350 ""}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk (Rise) clk (Rise) setup and hold " "From clk (Rise) to clk (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1540374952397 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1540374952397 ""}
|
||
|
|
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1540374952397 ""}
|
||
|
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540374952397 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540374952397 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 clk " " 20.000 clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1540374952397 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1540374952397 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node clk~input (placed in PIN T1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1540374952584 ""} } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5415 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1540374952584 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node reset_n~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1540374952584 ""} } { { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 368 -24 144 384 "reset_n" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 5416 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1540374952584 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1540374953178 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1540374953178 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1540374953178 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1540374953178 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1540374953194 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1540374953194 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1540374953194 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1540374953225 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1540374953225 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1540374953225 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1540374953225 ""}
|
||
|
|
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[0\] " "Node \"SDRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_BA\[1\] " "Node \"SDRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CKE " "Node \"SDRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_CLK " "Node \"SDRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[0\] " "Node \"SDRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_DQM\[1\] " "Node \"SDRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[0\] " "Node \"SDRAM_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[10\] " "Node \"SDRAM_D\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SDRAM_D\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1540374953490 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SDRAM_D\[11\] " "Node \"SDRAM_D\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin
|
||
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|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540374954209 ""}
|
||
|
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1540374954240 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1540374955412 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540374955959 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1540374955990 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1540374961412 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Fitter placement operations ending: elapsed time is 00:00:05" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540374961412 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1540374962162 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "44 X34_Y22 X44_Y32 " "Router estimated peak interconnect usage is 44% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32" { } { { "loc" "" { Generic "E:/cs208/quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 44% of the available device resources in the region that extends from location X34_Y22 to location X44_Y32"} { { 12 { 0 ""} 34 22 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1540374965240 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1540374965240 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1540375074577 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1540375074577 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1540375074577 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:51 " "Fitter routing operations ending: elapsed time is 00:01:51" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375074593 ""}
|
||
|
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 3.23 " "Total time spent on timing analysis during the Fitter is 3.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1540375075202 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1540375075233 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1540375075702 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1540375075702 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1540375076358 ""}
|
||
|
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1540375077139 ""}
|
||
|
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1540375077733 ""}
|
||
|
|
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "6 Cyclone IV E " "6 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 3.3-V LVTTL T1 " "Pin clk uses I/O standard 3.3-V LVTTL at T1" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 352 -24 144 368 "clk" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 138 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375077764 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "reset_n 3.3-V LVTTL AB11 " "Pin reset_n uses I/O standard 3.3-V LVTTL at AB11" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { reset_n } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "reset_n" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 368 -24 144 384 "reset_n" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375077764 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[0\] 3.3-V LVTTL B11 " "Pin in_buttons\[0\] uses I/O standard 3.3-V LVTTL at B11" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[0] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[0\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375077764 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[1\] 3.3-V LVTTL A11 " "Pin in_buttons\[1\] uses I/O standard 3.3-V LVTTL at A11" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[1] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[1\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1540375077764 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "in_buttons\[3\] 3.3-V LVTTL A12 " "Pin in_buttons\[3\] uses I/O standard 3.3-V LVTTL at A12" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { in_buttons[3] } } } { "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "in_buttons\[3\]" } } } } { "GECKO.bdf" "" { Schematic "E:/cs208/quartus/GECKO.bdf" { { 88 1328 1552 104 "in_buttons" "" } } } } { "temporary_test_loc" "" { Generic "E:/cs208/quartus/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design
|
||
|
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/cs208/quartus/GECKO.fit.smsg " "Generated suppressed messages file E:/cs208/quartus/GECKO.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1540375078077 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 60 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 60 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5646 " "Peak virtual memory: 5646 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540375079749 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 11:57:59 2018 " "Processing ended: Wed Oct 24 11:57:59 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540375079749 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:02:12 " "Elapsed time: 00:02:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540375079749 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:23 " "Total CPU time (on all processors): 00:02:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540375079749 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1540375079749 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1540375081342 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540375081342 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 11:58:01 2018 " "Processing started: Wed Oct 24 11:58:01 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540375081342 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1540375081342 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GECKO -c GECKO " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1540375081342 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1540375082327 ""}
|
||
|
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1540375083342 ""}
|
||
|
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1540375083576 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4707 " "Peak virtual memory: 4707 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540375084780 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 11:58:04 2018 " "Processing ended: Wed Oct 24 11:58:04 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540375084780 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540375084780 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540375084780 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1540375084780 ""}
|
||
|
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1540375085608 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1540375086639 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540375086639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 11:58:05 2018 " "Processing started: Wed Oct 24 11:58:05 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540375086639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1540375086639 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GECKO -c GECKO " "Command: quartus_sta GECKO -c GECKO" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1540375086639 ""}
|
||
|
|
{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1540375086936 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1540375087967 ""}
|
||
|
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1540375087967 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375088029 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375088029 ""}
|
||
|
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "The Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1540375088342 ""}
|
||
|
|
{ "Info" "ISTA_SDC_FOUND" "GECKO.sdc " "Reading SDC File: 'GECKO.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1540375088498 ""}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk (Rise) clk (Rise) setup and hold " "From clk (Rise) to clk (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1540375088545 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1540375088545 ""}
|
||
|
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1540375088545 ""}
|
||
|
|
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1540375088576 ""}
|
||
|
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1540375088779 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1540375088779 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.122 " "Worst-case setup slack is -3.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088795 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088795 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.122 -642.494 clk " " -3.122 -642.494 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088795 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375088795 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088842 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088842 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk " " 0.452 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088842 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375088842 ""}
|
||
|
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375088857 ""}
|
||
|
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375088873 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.624 " "Worst-case minimum pulse width slack is 9.624" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088889 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088889 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.624 0.000 clk " " 9.624 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375088889 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375088889 ""}
|
||
|
|
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1540375089061 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1540375089092 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1540375089810 ""}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk (Rise) clk (Rise) setup and hold " "From clk (Rise) to clk (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1540375090107 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1540375090107 ""}
|
||
|
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1540375090185 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1540375090185 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.929 " "Worst-case setup slack is -1.929" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.929 -259.589 clk " " -1.929 -259.589 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090217 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090217 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 clk " " 0.400 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090248 ""}
|
||
|
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375090264 ""}
|
||
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375090279 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.619 " "Worst-case minimum pulse width slack is 9.619" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.619 0.000 clk " " 9.619 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090295 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090295 ""}
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{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1540375090435 ""}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk (Rise) clk (Rise) setup and hold " "From clk (Rise) to clk (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1540375090685 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1540375090685 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.032 " "Worst-case setup slack is 10.032" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090732 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090732 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.032 0.000 clk " " 10.032 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090732 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090732 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk " " 0.186 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090764 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375090779 ""}
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{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1540375090795 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.207 " "Worst-case minimum pulse width slack is 9.207" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.207 0.000 clk " " 9.207 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1540375090810 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1540375090810 ""}
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{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1540375091623 ""}
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{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1540375091639 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4847 " "Peak virtual memory: 4847 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540375092045 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 11:58:12 2018 " "Processing ended: Wed Oct 24 11:58:12 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540375092045 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540375092045 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540375092045 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1540375092045 ""}
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{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 105 s " "Quartus Prime Full Compilation was successful. 0 errors, 105 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1540375093123 ""}
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